In one instance, the present invention is related generally to circuits and circuit layouts for logic circuits in which the logic circuit is protected against soft errors (non-destructive errors) and/or in which the effects of soft-errors are greatly reduced. The circuits and methods discussed herein may be particularly useful for complementary metal-oxide-semiconductor (CMOS) based logic circuits in modern technologies (≦90 nm). Unique circuit configurations as disclosed herein may protect the circuits against single event generated soft-errors.
Soft errors generated by single event transients (and single event upsets) are expected to increase drastically in ultra-deep submicron (<90 nm) technologies. Of particular significance is that logic circuits are expected to become much more sensitive to radiation generated soft-errors and possibly surpass memory as the major source of single event errors. Furthermore, the generation rate of multiple errors, multiple bit upsets (MBU), single-event multiple upset (SEMU) increases.
One reason for this increase is that, with a higher feature integration and higher frequencies, the spatial distribution and pulse length of a single event transient (SET) becomes become relatively larger, increasing the probability that an SET pulse is latched-in as a (soft-) error, or that SET pulses are generated simultaneously on several circuit nodes by one single event.
Increasing soft-error rates is further complicated by the escalating cost of semiconductor design and manufacturing. The high cost involved in developing and maintaining a semiconductor fabrication plant (FAB) makes it highly desirable to use standard commercial semiconductor manufacturing also for application that require a high radiation tolerance. Hence, there is a need to develop efficient and robust radhard-by-design (RHBD) techniques for these applications.
Furthermore, the design process is also becoming very complex and expensive, and it would be desirable to be able to re-use standard design intellectual property (IP) and libraries as much as possible for radhard applications.
Current radhard-by-design technology for single event errors include triplication (triple mode redundancy (TMR)), or duplication (built-in soft-error resilience (BiSER)) of circuits, combined some form of voting circuitry. These techniques generate undesirable power and area overhead, and current versions of these techniques cannot handle MBUs or SEMUs. Error correction codes (ECC) for memory, which also (loosely) could be classified as RHBD, is more efficient than duplication/triplication and can, with additional overhead, handle multiple errors in memory circuitry. However, the application of a corresponding error correction to logic circuits is very limited and application specific (e.g., selective parity check or insertion of specialized checking circuit IP).
State-of-the art for layout techniques for soft-error hard design mainly consist of simple spacing and sizing, and in adding additional contacts.
The inverse, or complement, of an output, or input, is the opposite value of the voltage of the circuit node with respect to the application. In a binary logic circuit each output or input is either high or low, represented by two different voltage values, which are the inverse of each other. Similarly for other application the inverse of a signal is defined by the states (or conditions) the circuit can be in.